A new IEEE standard to help track the testing of integrated circuits (ICs) from wafer to grave also offers an innovative new approach to combating the serious problem of IC counterfeiting.
Counterfeiters go after semiconductor chips because they’re big business. According to the Semiconductor Institute of America, worldwide chip sales in 2012 were almost $292 billion. Chips are also the foundation of the $1.1 trillion electronics industry. The price difference between a commercial temperature, low-speed IC and a military-temperature, high-speed IC can be tens, hundreds or even thousands of dollars. That significant difference is why counterfeiters erase the ink markings on a chip and re-mark it as a higher value part.
The losses from counterfeiting are impossible to determine with any degree of accuracy, but they are enormous. One report by supply chain participants cited 1,363 semiconductor counterfeiting incidents in 2011. A recent case involved a Florida firm that sold over $15 million of re-marked semiconductor chips to the United States Defense Department.
When lower speed, commercial-grade chips are re-marked by a counterfeiter and sold as high-speed, industrial chips for use in nuclear reactors or military-grade chips for weaponry, a counterfeit chip could have devastating consequences. This is also true when counterfeit electronic components are unwittingly placed in products used in the aviation, automotive, healthcare, data communications and other industries where reliability is critical.
The new IEEE standard being announced this month can stop the counterfeiting of ICs. IEEE Standard 1149.1™-2013 Standard Test Access Port and Boundary Scan Architecture provides new design-for-test guidance and two new hierarchical languages. One language describes the IEEE 1500 and IEEE 1149.1 design-for-test architecture residing in an IC. Boundary Scan Description Language links together the test access of embedded instrumentation known as Intellectual Property (IP). The second language, called Procedural Description Language (PDL), enables IP vendors to communicate how to operate on-chip IP via the 1149.1 test access port. The two standardized test languages eliminate the former “Tower of Babel” — the many languages used at various stages of testing throughout the life cycle of the IC.
The standard is designed to enable in-situ testing of an IC on an assembled circuit board with the same tests capable of running on the IC Automatic Test Equipment. Correlation between the two is achieved through a new on-chip Electronic Chip ID (ECID) register. The “die” — the actual silicon chip inside the IC — can be tracked to where it was created by the values in this special register. These include the manufacturing location, silicon wafer number and even the physical location on the particular wafer.
The standard also enables the ECID to be customized, extending it to add fields representing the speed and temperature grades of an IC.
C.J. Clark, who chaired the IEEE 1149.1-2013 Working Group, explains, “During the grading process, data representing the highest qualified speed and temperature for the IC is stored in the 1149.1-2013 accessible non-volatile memory. Since information is securely embedded into one-time programmable memory on each chip, the possibility for counterfeiting by re-marking a package is virtually eliminated.” He says potential buyers can use inexpensive tools to easily confirm that the ECID value read-out matches the markings on the package.”
He notes that ECID will also help to track stolen ICs the same way as serial numbers on a bank note. “Knowing what ECIDs are in a shipment will make it easier to track stolen ICs by reading the ECID and validating it against known stolen IDs,” he says.
Clark, who is also chief executive officer of Intellitech, which provides technology for testing semiconductors and electronic systems products through standards, says the new 1149.1-2013 also lowers industry costs through test re-use. “It enables knowledge transfer of how to operate on-chip IP such as a High-Speed SERDES I/O. The IP provider transfers it to their customer from the IC design engineer. Next, the IC vendor transfers the IP PDL routines to their customer, the system designer, who then passes it on to an in-house or outsourced test engineer,” he continues.
The standard was voted on by an IEEE Standards Association ballot group representing a cross section of the industry including Alcatel-Lucent, AMD, ARM, Cadence, Cisco, Freescale, Intel, NXP, ST Microelectronics, Synopsys, Texas Instruments and Teradyne, among others.
How can U.S. members get behind this significant new standard?
“One way to support it is at their place of work,” says Clark. “Members can encourage awareness of IEEE Standard 1149.1-2013 in the purchasing and incoming inspection departments at their companies. A contract requirement making compliance with this standard for system-on-a-chip and Application Specific ICs (ASICs) will help both the IC purchaser and the IC vendor.”
He predicts that once the new standard has gained a foothold, it would be realistic to expect that in five more years the majority of digital ICs will have ECID with speed, temperature and other grading information.”
Clark notes that the low-cost 1149.1-2013 approach is similar to how $20 bills are now authenticated. “You just hold it up to the light and see the embedded security thread,” he says. “The tools that use the standard to read out the ECID data are less than $250. This empowers the public to validate the authenticity — a formidable challenge to the counterfeiter who is just re-marking a lower-grade part.”--------------------